1. Field of the Invention
Generally, the present disclosure relates to the sophisticated integrated circuits including short channel transistor elements comprising highly capacitive gate structures on the basis of a metal-containing electrode material and a high-k gate dielectric of increased permittivity compared to conventional gate dielectrics, such as silicon dioxide and silicon nitride.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are based on silicon due to substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the dominant importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or other metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has continuously been decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current, while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, generally, the usage of high speed transistor elements having an extremely short channel may preferably be restricted to high speed signal paths, whereas transistor elements with a longer channel may be used for less critical circuit portions, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may nevertheless reach values for an oxide thickness in the range or 1-2 nm that may not be compatible with thermal design power requirements for performance driven circuits.
Therefore, replacing silicon dioxide as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. Therefore, it has been suggested to replace silicon dioxide with high permittivity materials such as tantalum oxide (Ta2O5) with a k of approximately 25, strontium titanium oxide (SrTiO3) having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
Additionally, transistor performance may be increased by providing an appropriate conductive material for the gate electrode to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance based on the same or greater thickness as a silicon dioxide layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, the non-polysilicon material, such as titanium nitride and the like, in combination with other metals, such as titanium, aluminum and the like, may be formed so as to connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone.
Since, typically, a low threshold voltage of the transistor, which represents the voltage at which a conductive channel forms in the channel region, is desired to obtain the high drive currents, commonly the controllability of the respective channel requires pronounced lateral dopant profiles and dopant gradients, at least in the vicinity of the PN junctions. Therefore, so-called halo regions are usually formed by ion implantation in order to introduce a dopant species whose conductivity type corresponds to the conductivity type of the remaining channel and semiconductor region to increase the resulting PN junction dopant gradient by this counter-doping in combination with respective extension and deep drain and source regions. In this way, the threshold voltage of the transistor significantly determines the controllability of the channel, wherein a significant variance of the threshold voltage may be observed for reduced gate lengths. Hence, by providing a precisely positioned halo or counter-doped implantation region in combination with well-controlled extension regions, the controllability of the channel may be enhanced, thereby also reducing the variance of the threshold voltage, which is also referred to as threshold roll-off, and also reducing significant variations of transistor performance with a variation in gate length.
Upon further reduction of the gate length, for instance for transistor elements having a gate length of approximately 40 nm and less, however, a significant variability of transistor characteristics may be observed and may be in part caused by a corresponding variability of the dopant profile of drain and source extension regions and the corresponding counter-doped regions. A corresponding pronounced variability may be caused by the material characteristics of the polysilicon material, which may act as an implantation mask during the sophisticated implantation sequence, as will be described in more detail with reference to FIGS. 1a-1d. 
FIG. 1a schematically illustrates a perspective view of a transistor element in a manufacturing stage prior to forming a complex dopant profile, which may include the implantation of a counter-doping species and a dopant species for drain and source extension regions, as explained above. As illustrated, the transistor 100 may comprise an active region 102 which may represent a portion of a semiconductor layer, such as a silicon layer, which may receive an appropriate dopant concentration profile so as to obtain the desired transistor behavior. The active region or semiconductor region 102 is provided above a substrate 101, which may represent a crystalline semiconductor material, an isolating material and the like. Moreover, a gate electrode structure 110 is formed on the active region 102 according to specific design dimensions, that is, the gate electrode structure 110 may have an average gate length as required by the design rules, which may be approximately 40 nm and less in extremely scaled semiconductor devices. The gate electrode structure 110 may comprise a gate insulation layer 111, which may represent a conventional dielectric material, such as silicon dioxide and the like, while, in other cases, sophisticated high-k dielectric materials may be used, as will be described later on in more detail. Furthermore, a polysilicon electrode material 112 is formed on the gate insulation layer 111 in accordance with well-established manufacturing strategies. As illustrated, the polysilicon material 112 may have a plurality of crystalline portions or grains 112A, 112N, which may have a different crystallographic orientation due to the polycrystalline nature of the material 112. Furthermore, due to the different crystallographic orientations of the various grains 112A, 112N, a pronounced “roughness” of sidewalls 112S of the material 112 may be created during the patterning of the material 112, which may be caused by a different etch behavior since, typically, corresponding grain boundaries may etch more efficiently compared to grain internal areas. The corresponding roughness of the sidewall 112S may be less critical for greater device dimensions and may, however, become increasingly important upon further device scaling since the intrinsic roughness of the material 112 may result in a corresponding variability of the complex dopant profiles.
That is, forming the gate electrode structure 110, may be accomplished by well-established manufacturing techniques for depositing or otherwise forming the gate insulation layer 111 and depositing the polysilicon material 112, for instance on the basis of well-established low pressure chemical vapor deposition (CVD) techniques, in order to obtain the polycrystalline state of the material 112, which may be advantageous in view of the conductivity of the material 112. Thereafter, sophisticated lithography techniques may be used in order to form a corresponding etch mask on the basis of which an appropriate sophisticated etch sequence may be performed to pattern the gate electrode material 112, thereby obtaining the configuration as shown in FIG. 1a. 
FIG. 1b schematically illustrates the transistor 100 during a sophisticated implantation sequence 103, during which drain and source extension regions 104 may be generated by incorporating an appropriate dopant species, wherein the gate electrode material 112 acts as an implantation mask. Furthermore, the sequence 103 may also comprise one or more implantation steps for incorporating a counter-doping species to form counter-doped or halo regions 105, which, in combination with the regions 104, may define a portion of a PN junction and may thus have a significant influence on the overall performance of the transistor 100, as discussed above. For this purpose, typically, the implantation sequence 103 may comprise implantation steps performed on the basis of a tilt angle, that is, a non-zero angle with respect to the surface normal of the active region 102 so that a corresponding ion species may also be positioned below the gate electrode within the active region 102. It should further be appreciated that the regions 104 may be formed on the basis of a tilted implantation process, if required, for instance when an asymmetric configuration may have to be formed for the extension regions 104 and the like. Consequently, during the sequence 103, the electrode material 112 may “shadow” a portion of the active region 102, wherein a corresponding roughness of the sidewalls 112S (FIG. 1a) may be “imaged” in a more or less diffused manner into a corresponding implantation profile.
FIG. 1c schematically illustrates a corresponding effect of the line roughness of the material 112 along the transistor width direction, indicated as W. It should be appreciated that, for convenience, the gate electrode material 112 is not shown in FIG. 1c. In addition to the variability of the dopant profiles along the transistor width direction caused by the initial roughness of the material 112, an additional contribution to dopant variability may be caused by the polycrystalline nature of the material 112. That is, a varying degree of channeling may occur during the preceding implantation sequence, in particular during the preceding tilted implantation steps. That is, if the direction of an ion beam impinging a material may be in close proximity to a major crystallographic axis of the material, the penetration behavior may significantly differ from a penetration into a disordered material since the positive ions, when encountering a corresponding potential created by a crystallographic axis, may suffer from a significantly reduced degree of interaction, thereby penetrating deeply into the depth of the material. Consequently, due to the presence of the plurality of different crystallographic orientations of the various grains 112A, 112N (FIG. 1a), the channeling effect may also vary along the transistor width direction, thereby further contributing to the corresponding variability of the dopant profile due to a varying lateral and vertical penetration depth.
FIG. 1d schematically illustrates the effect of a varying channeling behavior.
Since both effects, i.e., the initially created line roughness and the different channeling effect may be independent of each other, both effects may result in an even further pronounced dopant variability, which may thus significantly affect the resulting transistor performance, as explained above.
Thus, upon further scaling the gate length of transistor elements, this effect may become more pronounced and may also have a significant influence on transistor elements in which additional performance enhancing mechanisms may be implemented, such as a sophisticated gate electrode structure, possibly in combination with strain-inducing mechanisms, as will be described in more detail with reference to FIGS. 1e-1n. 
FIG. 1e schematically illustrates a cross-sectional view of a semiconductor device 150 comprising an N-channel transistor 100A and a P-channel transistor 100B at an early manufacturing stage. In this manufacturing stage, a sophisticated layer stack is formed above the semiconductor layer 102, which may comprise appropriate active regions 102A, 102B for the transistors 100A, 100B. The layer stack may comprise a gate insulation layer 111 comprising a high-k dielectric material, which may be one or more of the above-mentioned materials, possibly in combination with a conventional dielectric material, such as silicon dioxide and the like. Furthermore, a metal-containing material may be formed on the gate insulation layer 111 which may comprise any appropriate metal-containing material or combinations of different metal species so as to obtain an appropriate work function for the transistor 100A, which may be important for adjusting transistor characteristics, such as the threshold voltage, in combination with a sophisticated dopant profile, as explained above. Furthermore, a conductive barrier material 120P, such as titanium nitride and the like, may be formed on an electrode material 112O. Moreover, a silicon-based electrode material 112Q may be formed on the barrier layer 120P. Additionally, an etch mask 106 is formed above the active regions 102A, 102B to define the lateral position and size of a gate electrode structure still to be formed on the basis of the underlying materials. It should be appreciated that the semiconductor device 150 according to FIG. 1e may represent a sophisticated manufacturing strategy for providing a high-k metal gate configuration at an early manufacturing stage, which may be patterned on the basis of the mask 106 and may not require any further material replacement at a later manufacturing stage. In this case, the work function defined by the electrode material 112O may not be appropriate for the transistor 100B and thus typically a semiconductor alloy 120C may be formed on the active region 102B in order to provide a desired band gap offset to obtain an appropriate threshold voltage in combination with the material 112O. For example, a silicon/germanium alloy with a specified thickness and germanium concentration may be used.
The semiconductor device 150 as shown in FIG. 1e may be formed on the basis of well-established process techniques, i.e., the semiconductor layer 120C may be formed on the basis of epitaxial growth techniques, wherein a corresponding growth on the active region 102A may be avoided by providing an appropriate growth mask. Thereafter, the gate insulation layer 111 may be formed by deposition and the like, followed by the deposition of the electrode material 112O, which may include a plurality of separate deposition steps, depending on the complexity of the material 112O. Thereafter, the barrier layer 120P may be formed, for instance, by sputter deposition, CVD and the like, followed by the deposition of the material 112Q in the form of a silicon material, which may be provided in the form of an amorphous silicon material due to its reduced thickness and due to moderately low deposition temperatures used. Thereafter, the etch mask 106 may be formed on the basis of well-established lithography techniques.
FIG. 1f schematically illustrates the semiconductor device 150 according to a further alternative manufacturing strategy in which a high-k dielectric material is provided in an early manufacturing stage, while a metal-containing material may be formed after completing the basic transistor configuration. In this case, the transistors 100A, 100B may have substantially the same configuration except for the conductivity type of the active regions 102A, 102B. That is to say, the gate insulation layer 111 comprising the high-k dielectric material may be formed on the active regions 102A, 102B, followed by a metal-containing barrier material, such as titanium nitride and the like, indicated as 112P, which may also be used in the device 150 of FIG. 1e. Furthermore, the silicon material 112, which may be replaced in a later manufacturing stage, may be provided in a polycrystalline state in conformity with well-established manufacturing techniques.
FIGS. 1g and 1h schematically illustrate the semiconductor device 150 of FIGS. 1e and 1f, respectively, in a further advanced manufacturing stage. As illustrated, the device 150 of FIG. 1g may comprise gate electrode structures 100A, 100B, respectively, which may include the complex layer stack as described with reference to FIG. 1e, wherein, in particular, the amorphous material 112Q may be present. Similarly, the gate electrode structures 100A, 100B of the device 150 of FIG. 1h may include the polysilicon material 112 of the corresponding patterning sequence.
FIGS. 1i and 1j schematically illustrate the semiconductor devices 150 of FIGS. 1g and 1h, respectively, in a further advanced manufacturing stage. As illustrated, a sidewall liner material 113 may be formed on sidewalls of the gate electrode structures 100A, 100B to provide integrity of the sensitive high-k gate insulation layer 111 during the further processing. As is well known, during the fabrication of complex semiconductor devices, a plurality of wet chemical etch steps may have to be performed, for instance, in view of cleaning surface areas, removing resist material and the like. Frequently, well-established chemical agents, such as diluted hydrofluoric acid (HF) and the like, may be used for removing contaminants and silicon dioxide-based material with high efficiency. Similarly, a mixture of sulphuric acid and hydrogen peroxide may frequently be used for removing resist materials. These well-approved chemical agents may, however, result in a significant material erosion of the high-k materials so that a corresponding protection of any exposed surface areas thereof may be required. For this purpose, typically, the liner material 113 may be formed on the basis of silicon nitride with a thickness of one to several nanometers, which may be accomplished on the basis of sophisticated thermally activated CVD techniques at a temperature of 600° C. and less, followed by an anisotropic etch step for removing the material from horizontal device portions.
FIGS. 1k and 1l schematically illustrate the semiconductor device 150 of FIGS. 1i and 1j, respectively, in a further advanced manufacturing stage in which a strain-inducing mechanism may be established, at least in one of the transistors 100A, 100B in accordance with well-established strategies. As illustrated, the transistors 100A in FIGS. 1k and 1l may be covered by a spacer layer 107, such as a silicon nitride layer, while the transistors 100B may have formed a corresponding sidewall spacer element 107B on sidewalls of the gate electrode structures 100B. Furthermore, a silicon/germanium alloy 108 is formed in the active regions 102B in FIGS. 1k and 1l in order to induce a desired type of strain, such as a compressive strain, below the gate electrode structures 100B. As is well known, a certain type of strain may significantly modify the charge carrier mobility of a silicon-based semiconductor material so that, upon appropriate selection of a strain component, overall transistor performance may be enhanced. In the example shown, P-channel transistors 100B may receive enhanced charge carrier mobility and thus an increased drive current upon creating a compressive strain below the gate electrode structures 100B.
The semiconductor devices 150 of FIGS. 1k and 1l may be formed on the basis of the following processes. First, the spacer layer 107 may be deposited by well-established thermally activated CVD techniques in which typically a moderately high temperature of above 600° C. may have to be applied in order to obtain a desired high material density so as to withstand an etch attack of an etch chemistry to be used for forming corresponding cavities in the transistors 100B in a further advanced manufacturing stage. Thus, during this deposition process performed on the basis of elevated temperatures, the material 112Q (FIG. 1g) may be converted into a polysilicon material, indicated as 112 in the device 150 of FIG. 1k. As previously discussed, due to the polycrystalline nature, a corresponding pronounced line edge roughness may be created. After the deposition of the spacer layer 107, the transistors 100A may be masked by a resist material and an anisotropic etch process may be performed to obtain the spacer elements 107B in the transistors 100B. After removal of the resist mask, cavities (not shown) may be formed in the transistors 100B, while the mask 107 and the spacers 107B, possibly in combination with the mask material formed on the material 112 (not shown), may act as an etch mask. In other cases, the material of the gate electrode material 112 may be removed during the corresponding etch process. Next, a selective epitaxial growth process may be performed, thereby depositing the silicon/germanium alloy 108 in a strained state.
FIGS. 1m and 1n schematically illustrate the semiconductor device 150 of FIGS. 1k and 1l, respectively, in a further advanced manufacturing stage. As illustrated, the device 150 is subjected to an implantation sequence 103 in order to form corresponding extension regions 104A, 104B and halo regions 105A, 105B, respectively. It should be appreciated that the implantation sequence 103 may comprise the corresponding masking regime for separately introducing an appropriate dopant species and counter-dopant species into the active regions 102A and 102B.
As previously discussed with reference to FIGS. 1a-1d, the polycrystalline nature of the material 112 may result in a significant variation of the dopant profile along the transistor width direction. For this purpose, frequently, an offset spacer 109 may be formed on sidewalls of the gate electrode structures 100A, 100B after the removal of the spacer layer 107 and the spacer element 107B (FIGS. 1k, 1l). The offset spacer elements 109, such as silicon dioxide spacers and the like, may be deposited with an appropriate thickness so as to at least significantly reduce the channeling effect caused by the polycrystalline material which, however, may require a specific width of the spacer elements 109. On the other hand, the pronounced variability of thickness, i.e., the line edge roughness previously discussed, may be even further pronounced by additional thickness variations during the deposition of a corresponding spacer material for the sidewall spacers 109. Thus, although the degree of channeling may be reduced, however, at the cost of an additional “blurring” of the incoming ion beam, a further pronounced variability of the resulting dopant profiles of the extension regions 104A, 104B and the counter-doped regions 105A, 105B may be created.
Consequently, upon further processing of the device 150, a corresponding variability of transistor characteristics may also be created in the finalized transistors 100A, 100B, irrespective of whether the approach of providing the sophisticated gate electrode structures 110A, 110B on the basis of the complex layer stack as shown in FIG. 1e, or the approach of replacing the material 112 in a very advanced manufacturing stage may be taken.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.